1. Field of the Invention
The present invention relates to a signal processing circuit of a video camera for synchronously operating a plurality of video cameras suitable for building a security system.
2. Description of the Prior Art
A security system with video cameras installed in rooms for monitoring their interiors from a remote location has been widely used. To build such a security system, it is necessary to synchronously operate the video cameras to prevent loss of synchronism when switching from video camera to another.
To synchronously operate the video cameras, it is necessary to supply a common synchronizing signal from a controller to each of the video cameras. However, in the countries where the frequency of the AC utility power accords with the field frequency of the television system, for example, the United States, by using the AC utility power, the video cameras can be synchronously operated without the synchronous signal supplied from the controller thereto. The method of synchronously operating the video cameras with the AC utility power is called AC lock.
FIGS. 1 and 2 show an example of conventional video camera systems which synchronously operate a plurality of video cameras by using the AC utility power. In the example, the frequency of the AC utility power is 60 Hz and a television system with a field frequency of 60 Hz is used.
FIG. 1 shows an example of an image pick-up tube. In the figure, reference numeral 51 is a synchronism generation counter for generating a vertical pulse signal V.sub.PLS and a horizontal pulse signal H.sub.PLS. The synchronism generation counter 51 counts the number of pulses of a reference clock signal CK (for example, of frequency 4 f.sub.sc of where f.sub.sc =14.3 MHz) so as to form the horizontal pulse signal H.sub.PLS and the vertical pulse signal V.sub.PLS. A vertical reset signal is supplied from a wave form shaping circuit 53 to the synchronism generation counter 51.
The horizontal pulse signal H.sub.PLS and the vertical pulse signal V.sub.PLS are supplied from the synchronism generation counter 51 to a deflection circuit 52. The deflection circuit 52 forms sawtooth waves for horizontal deflection and vertical deflection in accordance with the horizontal pulse signal H.sub.PLS and the vertical pulse signal V.sub.PLS supplied from the synchronism generation counter 51. The output signal of the deflection circuit 52 is supplied to an image pick-up tube 54. The image pick-up tube 54 scans an electron beam in accordance with the output signal of the deflection circuit 52.
The image pick-up tube 54 images an object. The output signal of the image pick-up tube 54 is supplied to a video signal processing circuit 55. The video signal processing circuit 55 adds a composite synchronizing signal from the synchronism generation counter 51 to the output signal of the image pick-up tube 54, thereby forming a video signal for the television system having a field frequency of 60 Hz. The video signal is obtained from an output terminal 56.
A source of AC utility power 57 at a frequency of 60 Hz is supplied to the waveform shaping circuit 53. The waveform shaping circuit 53 forms a pulse signal at a frequency of 60 Hz in accordance with the phase of the AC utility power source 57. The 60 Hz pulse signal is supplied to a vertical reset terminal of the synchronism generation counter 51.
The 60 Hz pulse signal from the waveform shaping circuit 53 causes the synchronism generation counter to be reset. Thus, the vertical phase of the video signal is forcedly synchronized with the phase of the AC utility power 57.
FIG. 2 shows an example of using a solid state imaging device. In the figure, a synchronism generation counter 61 counts the number of pulses of a reference clock signal CK so as to generate a field distinction signal S.sub.F as well as the horizontal pulse signal H.sub.PLS and the vertical pulse signal V.sub.PLS. The horizontal pulse signal H.sub.PLS, the vertical pulse signal V.sub.PLS, and the field distinction signal S.sub.F are supplied to a clock driver 62. The clock driver 62 generates a horizontal transfer clock signal and a vertical transfer clock signal in accordance with the horizontal pulse signal H.sub.PLS and the vertical pulse signal V.sub.PLS, respectively. The horizontal transfer clock and the vertical transfer clock are supplied to a solid state imaging device 64 which is a CCD imaging device or the like.
The solid state imaging device 64 images an object. The output signal of the solid state imaging device 64 is supplied to a video signal processing circuit 65. The video signal processing circuit 65 adds a composite synchronizing signal from the synchronism generation counter 61 to the output signal of the solid state imaging device 64, thereby forming a video signal for a television system having a field frequency of 60 Hz. The video signal is obtained from an output terminal 66.
The waveform shaping circuit 63 shapes the wave form of an AC utility power source 67 and forms a 60 Hz pulse signal. The 60 Hz pulse signal is supplied to the synchronism generation counter 61 as a reset signal.
The synchronism generation counter 61 receives the reset signal from the waveform shaping circuit 63. Thus, the synchronism generation counter 61 is forcedly reset in accordance with the 60 Hz AC utility power. Thus, the vertical phase of the video signal is forcedly synchronized with the phase of the AC utility power.
In the video signal processing circuits shown in FIG. 1 and FIG. 2, the synchronism generation counters 51 and 61 are forcedly reset by the output signals of the waveform shaping circuits 53 and 63 for shaping the waveforms of the AC utility power sources 57 and 67, respectively. Thus, the vertical phase is synchronized with the phase of the AC utility power.
However, the frequency and the amplitude of the AC utility power are not strictly controlled and thereby distortions of phase and amplitude take place.
In the conventional video processing circuits shown in FIGS. 1 and 2, when the AC utility power sources 57 and 67 have a time base fluctuation, the number of horizontal scanning lines varies in each field and thereby a vertical jitter occasionally takes place.
In the example of the imagine pick-up tube 54 shown in FIG. 1, when the AC utility power source 57 has a time base fluctuation, the number of scanning lines of an even field of a frame can become the same as that of the odd field, and thereby interlaced scanning cannot be achieved. Thus, the imaging resolution degrades and the video signal cannot be recorded to a VTR.
In the example of using the solid state imaging device 64 shown in FIG. 2, when the AC utility power source 67 has a time base fluctuation, thereby causing the number of scanning lines of an even field becomes the same as that of an odd field, the vertical shift register cannot be switched between the even field and the odd field. Thus, the solid state imaging device 64 does not operate. To prevent that, it is necessary to structure the clock driver 62 with a PLL (Phase-Locked Loop) system. However, such a PLL system should be a high speed device. Thus, when the clock driver 62 is embodied with a PLL structure, its cost increases markedly.
In addition, in the United States, a single-phase, 24 V AC utility power source is supplied for a security system. However, the selection of which phase is to be used for the single-phase, 24 V AC utility power is not always controlled due to the purpose of the application. Thus, when the three-phase AC power is converted into the single phase AC power, the obtained phase of the utility power may differ at different outlet of the same housing different phases.
When the AC-lock is performed with utility power sources whose phases differ from each other, the vertical phase of the video signal differs in each camera. Thus, when one camera is switched to another one, loss of synchronism takes place.